Optimization of SCR for High-Speed Digital and RF Applications in 45-nm SOI CMOS Technology
Author:
Affiliation:
1. University of Illinois at Urbana-Champaign,Department of Electrical and Computer Engineering,Urbana,IL,USA,61801
2. Analog Devices, Inc.,Wilmington,MA,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10117589/10117581/10118266.pdf?arnumber=10118266
Reference14 articles.
1. Time-dependent snapback in thin-film SOI MOSFET's
2. An investigation of ESD protection diode options in SOI
3. Physical Basis for CMOS SCR Compact Models
4. A Scalable SCR Compact Model for ESD Circuit Simulation
5. A physics-based compact model for SCR devices used in ESD protection circuits
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