A cost-effective 0.25 μm L/sub eff/ BiCMOS technology featuring graded-channel CMOS (GCMOS) and a quasi-self-aligned (QSA) NPN for RF wireless applications

Author:

Chai F.K.,Kyono C.,Ilderem V.,Kaneshiro M.,Zupac D.,Bigelow S.,Ramiah C.,Dahl P.,Braithwaite R.,Morgan D.,Hildreth S.,Grynkewich G.

Publisher

IEEE

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Physics, Technology, and Modeling of Complementary Asymmetric MOSFETs;IEEE Transactions on Electron Devices;2010-10

2. High-<tex>$Q$</tex>Electrostatic Discharge (ESD) Protection Devices for Use at Radio Frequency (RF) and Broad-band I/O Pins;IEEE Transactions on Electron Devices;2005-07

3. Comprehensive ESD protection for RF inputs;Microelectronics Reliability;2005-02

4. Design and Optimization of Vertical SiGe Thyristors for On-Chip ESD Protection;IEEE Transactions on Device and Materials Reliability;2004-12

5. Simulation of oxide trapping noise in submicron n-channel MOSFETs;IEEE Transactions on Electron Devices;2003-03

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