1. Low Power Multiplier Using Approximate Adder for Error Tolerant Applications;IETE Journal of Research;2024-09-11
2. Design of FIR Filter Using a Novel Approach with High-Speed Multiplier;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28
3. High Speed 64 Bit Vedic & Booth Multiplier Implementation Using FPGA;2024 3rd International Conference on Artificial Intelligence For Internet of Things (AIIoT);2024-05-03
4. Design and Implementation of Optimized FIR Filter using CSA and Booth Multiplier for High Speed Signal Processing;2023 4th International Conference for Emerging Technology (INCET);2023-05-26
5. Vedic Multiplier for High-Speed Applications;Communication, Software and Networks;2022-10-28