Machine Learning-Based Modeling of Hot Carrier Injection in 40 nm CMOS Transistors
Author:
Affiliation:
1. LIRMM, CNRS, Montpellier, France
2. Department of Electronics and Communications Engineering, Istanbul Technical University, Istanbul, Turkey
Funder
Technological Research Council of Turkey through Project TÜB˙ITAK 1001
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/6245494/10416702/10477498.pdf?arnumber=10477498
Reference22 articles.
1. Surrogate-Model-Based Analysis of Analog Circuits—Part II: Reliability Analysis
2. Review: Analog design methodologies for reliability in nanoscale CMOS circuits
3. Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology
4. Holistic Device Modeling: Toward a Unified MOSFET Model Including Variability, Aging, and Extreme Operating Conditions
5. Cross-Layer Modeling and Simulation of Circuit Reliability
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