The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures

Author:

Salerno Galembeck Egon Henrique1ORCID,Renaux Christian2,Swart Jacobus Willibrordus3,Flandre Denis2ORCID,Gimenez Salvador Pinillos1ORCID

Affiliation:

1. Department of Electrical Engineering, FEI University Center, São Bernardo do Campo, São Paulo, Brazil

2. ICTEAM Institute, Université Catholique de Louvain, Louvain-La-Neuve, Belgium

3. FEEC/UNICAMP, UNICAMP University, Campinas, Brazil

Funder

São Paulo Research Foundation

Conselho Nacional de Desenvolvimento Científico e Tecnológico

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials,Biotechnology

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Introduction;Differentiated Layout Styles for MOSFETs;2023

2. Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET;2022 36th Symposium on Microelectronics Technology (SBMICRO);2022-08-22

3. Impact of using Octogonal Layout Style in Planar Power MOSFETs;2022 36th Symposium on Microelectronics Technology (SBMICRO);2022-08-22

4. New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs;IEEE Transactions on Electron Devices;2022-06

5. The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs;2021 35th Symposium on Microelectronics Technology and Devices (SBMicro);2021-08-23

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