3-D Monolithic Stacking of Complementary-FET on CMOS for Next Generation Compute-In-Memory SRAM-Reference-Cited by-同舟云学术

3-D Monolithic Stacking of Complementary-FET on CMOS for Next Generation Compute-In-Memory SRAM

Published:2023 Issue: Volume:11 Page:107-113
ISSN:2168-6734
Container-title:IEEE Journal of the Electron Devices Society
language:
Short-container-title:IEEE J. Electron Devices Soc.

Author:

Baig Md. Aftab¹^ORCID,Yeh Cheng-Jui¹,Chang Shu-Wei²,Qiu Bo-Han¹,Huang Xiao-Shan¹,Tsai Cheng-Hsien¹,Chang Yu-Ming¹,Sung Po-Jung³,Su Chun-Jung⁴,Cho Ta-Chun³^ORCID,De Sourav¹^ORCID,Lu Darsen¹^ORCID,Lee Yao-Jen⁵^ORCID,Lee Wen-Hsi²^ORCID,Wu Wen-Fa³^ORCID,Yeh Wen-Kuan³

Affiliation:

1. Institute of Microelectronics, National Cheng Kung University, Tainan, Taiwan

2. Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan

3. Taiwan Semiconductor Research Institute, Hsinchu, Taiwan

4. Department of Electrophysics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

5. Institute of Pioneer Semiconductor Innovation, Industry Academia Innovation School, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

Funder

Ministry of Science and Technology

Center for Future Computing, Miin Wu School of Computing, NCKU

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials,Biotechnology

Link

http://xplorestaging.ieee.org/ielx7/6245494/10049274/09999326.pdf?arnumber=9999326

Reference20 articles.

1. Robust Binary Neural Network Operation From 233 K to 398 K via Gate Stack and Bias Optimization of Ferroelectric FinFET Synapses

2. Robust SRAM Designs and Analysis

3. 3-D self-aligned stacked NMOS-on-PMOS nanoribbon transistors for continued Moore’s law scaling;huang;Proc IEEE Int Electron Devices Meeting (IEDM),2020

4. New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing