Performance Evaluation of Buried Gate Oxide based Negative Capacitance FinFETs
Author:
Affiliation:
1. PDPM IIITDM Jabalpur,Department of Electronics and Communication Engineering,Jabalpur,India,482005
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10134754/10134560/10135009.pdf?arnumber=10135009
Reference25 articles.
1. Demonstration of Improved Short Channel Performance Metrics for Ferroelectric Concentric Negative Capacitance FinFET;chauhan;Silicon,2022
2. Exploration and Device Optimization of Dielectric–Ferroelectric Sidewall Spacer in Negative Capacitance FinFET
3. DIBL enhancement in ferroelectric-gated FinFET
4. Experimental observation of zero DIBL in short-channel hysteresis-free ferroelectric-gated FinFET
5. Sub-20nm gate length FinFET design: Can high-k spacers make a difference;sachid;IEEE Trans Electron Devices,2008
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Impact of Buried Gate Oxide on the Electrical Performance of Negative Capacitance FinFETs: Design Perspectives;Silicon;2024-02-16
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