Gate Engineered IGBT with Improved Device Performance-Reference-Cited by-同舟云学术

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Gate Engineered IGBT with Improved Device Performance

Published:2023-04-07 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Devices for Integrated Circuit (DevIC)
language:
Short-container-title:

Author:

Sahu Satish Kumar¹,Parmar Onika²,Chacko Saji. T.³,Rajput Amit Singh²

Affiliation:

1. Chhattisgarh Swami Vivekanand Technical University,Dept. of Electrical Engineering,Bhilai,India

2. Chhattisgarh Swami Vivekanand Technical University,Dept. of Microelectronics and VLSI,Bhilai,India

3. Uday Prasad Govt. Polytechnic, Durg Durg,Dept. of Electrical Engineering,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10134754/10134560/10134985.pdf?arnumber=10134985

Reference20 articles.

1. A Low On-State Voltage and Saturation Current TIGBT With Self-Biased pMOS

2. Trench Shielded Planar Gate IGBT (TSPG-IGBT) With Self-Biased pMOS Realizing Both Low On-State Voltage and Low Saturation Current

3. Atlas User's Manual-Device Simulation Software-Silvaco,2013

4. Simulation Study of 4H-SiC Trench Insulated Gate Bipolar Transistor with Low Turn-Off Loss

5. Evaluation of Ultrahigh-Voltage 4H-SiC Gate Turn-OFF Thyristors and Insulated-Gate Bipolar Transistors for High-Power Applications

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