Analytical Modeling of Asymmetric Junctionless Dual Material Double Gate MOSFET with Underlap for Enhanced Hot Carrier Reliability-Reference-Cited by-同舟云学术

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Analytical Modeling of Asymmetric Junctionless Dual Material Double Gate MOSFET with Underlap for Enhanced Hot Carrier Reliability

Published:2023-04-07 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Devices for Integrated Circuit (DevIC)
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Short-container-title:

Author:

Basak Arighna¹,Deyasi Arpan²,Sarkar Angsuman³

Affiliation:

1. Brainware University,Department of Electronics and Communication Engineering,Barasat,India

2. RCC Institute of Information Technology,Department of Electronics and Communication Engineering,Kolkata,India

3. Kalyani Govt Engg College,Department of Electronics and Communication Engineering,Kalyani,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10134754/10134560/10134835.pdf?arnumber=10134835

Reference41 articles.

1. Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE

2. Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion

3. Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs

4. Simulation and comparative study on analog/RF and linearity performance of III–V semiconductor-based staggered heterojunction and InAs nanowire(nw) Tunnel FET

5. Analytical Model of Subthreshold Current and Slope for Asymmetric 4-T and 3-T Double-Gate MOSFETs

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