Analysis of SiGe, InGaAs and GaN on 5nm MOSFET Modelling with Applications
Author:
Affiliation:
1. University of Kalyani,Department of Computer Science and Engineering,Kalyani,India
2. University of Kalyani (in lien),Raiganj University, Department of Computer Science and Engineering,Kalyani,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10134754/10134560/10134976.pdf?arnumber=10134976
Reference14 articles.
1. Statistical process modelling for 32 nm high-K/Metal gate PMOS device;maheran;Proceedings of IEEE-ICSE,2014
2. Comparison of drive currents in metal-oxide-semiconductor field-effect transistors made of Si, Ge, GaAs, InGaAs, and InAs channels;abigail;Applied Physics Letters,2010
3. Analysis of noise margin of CMOS inverter in sub-threshold regime
4. Effects of High-K Dielectrics with metal gate for electrical characteristics of 18 nm NMOS device;atan;IEEEICSEProc,2014
5. III-V Junctionless Gate-All-Around Nanowire MOSFETs for High Linearity Low Power Applications
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