Performance Analysis of Low Power Multiplexer for Communication System

Author:

Rai Lalit1,Kumar Prashant1,Gupta Neeraj2,Gupta Rashmi2

Affiliation:

1. J.C. Bose University of Science &Technology YMCA, Faridabad,Dept. of Electronics Engineering,Faridabad,India,121006

2. Amity University,Amity School of Engineering & Technology,Dept. of Electronics & Communication Engineering,Haryana,Gurugram,India,122413

Publisher

IEEE

Reference8 articles.

1. Design and Implementation of optimized 4:1 Multiplexer using Adiabatic Technique;kamboj;International Journal of Advance Research in Science and Engineering IJARSE,2014

2. High performance, low power 200 Gb/s 4:1 MUX with TGL in 45 nm technology

3. Comparative Analysis of a NAND Gate and a 2-Bit Magnitude Comparator Using GDI Technique;achu mathew;International Conference on Emerging Trends and Innovations in Engineering and Technological Research (ICETIETR),2018

4. Top-down pass-transistor logic design

5. Multiple logic styles for low power 4:1 multiplexer in 45 nm technology

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