Author:
Kulkarni Samarth J.,Murty N.S.
Cited by
7 articles.
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1. Implement a PnR Flow to Boost the Pin Density in Block Level Chip Design;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28
2. Design of PnR Flow For Block Level Chip for Optimizing Leakage Power;2024 Third International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS);2024-03-14
3. Congestion Hotspots Identification and Mitigation Suggestions Through Design File;2024 IEEE International Conference for Women in Innovation, Technology & Entrepreneurship (ICWITE);2024-02-16
4. Methodology for Timing Closure in VLSI Physical Design containing high clock to Q Memory Delay;2023 IEEE Silchar Subsection Conference (SILCON);2023-11-03
5. An Efficient Metal ECO Methodology for Addressing Timing Violations with 10X Turnaround Time;2022 3rd International Conference on Smart Electronics and Communication (ICOSEC);2022-10-20