Cost analysis study of variable parallel prefix adders using altera cyclone IV FPGA kit

Author:

Marouf Ibrahim,Asad Mohammed Mosab,Bakhuraibah Ahmad,Al-Haija Qasem Abu

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of Brent Kung Prefix Form Carry Look Ahead Adder;2022 8th International Conference on Wireless and Telematics (ICWT);2022-07-21

2. A High-Performance Wide FPGA Adder Based on Carry Chains;Proceedings of the 2020 4th International Conference on Electronic Information Technology and Computer Engineering;2020-11-06

3. Pipelined Implementation of Millar-Rabin Primality Tester Using Altera FPGA Kit;Communications in Computer and Information Science;2020

4. Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications;Advances in Science, Technology and Engineering Systems Journal;2019

5. Design and analysis of high-speed 8-bit ALU using 18 nm FinFET technology;Microsystem Technologies;2018-09-04

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