Massive Parallel-Hardware Architecture for Multiscale Stereo, Optical Flow and Image-Structure Computation

Author:

Tomasi Matteo,Vanegas Mauricio,Barranco Francisco,Daz Javier,Ros Eduardo

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Media Technology

Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An efficient real-time accelerator for high-accuracy DNN-based optical flow estimation in FPGA;Journal of Systems Architecture;2023-03

2. Using HLS for Designing a Parametric Optical Flow Hierarchical Algorithm in FPGAs;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

3. FPGA Acceleration of the Horn and Schunck Hierarchical Algorithm;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05

4. Scalable Architecture for High-Resolution Real-time Optical Flow Processor;2019 IEEE International Conference on Internet of Things and Intelligence System (IoTaIS);2019-11

5. Architectures for Stereo Vision;Handbook of Signal Processing Systems;2018-10-14

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