Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder-Reference-Cited by-同舟云学术

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Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

Published:2006-06 Issue:6 Volume:16 Page:673-688
ISSN:1051-8215
Container-title:IEEE Transactions on Circuits and Systems for Video Technology
language:
Short-container-title:IEEE Trans. Circuits Syst. Video Technol.

Author:

Tung-Chien Chen ,Shao-Yi Chien ,Yu-Wen Huang ,Chen-Han Tsai ,Ching-Yeh Chen ,To-Wei Chen ,Liang-Gee Chen

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Media Technology

Link

http://xplorestaging.ieee.org/ielx5/76/34319/01637509.pdf?arnumber=1637509

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3. Low-Complexity Hardware Architecture of an H.264-Based Video Encoder for FPGAs;2023 Congress in Computer Science, Computer Engineering, & Applied Computing (CSCE);2023-07-24

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