A low-power hybrid reconfigurable architecture for resistive random-access memories
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7440961/7446041/7446057.pdf?arnumber=7446057
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Optimizing multi-level ReRAM memory for low latency and low energy consumption;it - Information Technology;2023-05-01
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4. A Low Power Reconfigurable Memory Architecture for Complementary Resistive Switches;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-09
5. R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-11
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