Author:
Yoon Doe Hyun,Muralimanohar Naveen,Chang Jichuan,Ranganathan Parthasarathy,Jouppi Norman P.,Erez Mattan
Cited by
106 articles.
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1. Soft and Hard Error-Correction Techniques in STT-MRAM;IEEE Design & Test;2024-10
2. Achieving DRAM-Like PCM by Trading Off Capacity for Latency;IEEE Transactions on Computers;2024-04
3. SELCC: Enhancing MLC Reliability and Endurance with Single-Cell Error Correction Codes;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
4. Mitigating Write Disturbance in Non-Volatile Memory via Coupling Machine Learning with Out-of-Place Updates;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02
5. Hard Error Correction in STT-MRAM;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22