Author:
Shin Wongyu,Yang Jeongmin,Choi Jungwhan,Kim Lee-Sup
Cited by
33 articles.
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1. FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration;ACM Transactions on Architecture and Code Optimization;2024-05-21
2. CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-09
3. A Hardware-Based Approach to Determine the Frequently Accessed DRAM Pages for Multi-Core Systems;2023 IEEE Jordan International Joint Conference on Electrical Engineering and Information Technology (JEEIT);2023-05-22
4. A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-01
5. Scalable Deep Learning-Based Microarchitecture Simulation on GPUs;SC22: International Conference for High Performance Computing, Networking, Storage and Analysis;2022-11