Author:
Abeyratne N.,Das R.,Qingkun Li ,Sewell K.,Giridhar B.,Dreslinski R. G.,Blaauw D.,Mudge T.
Cited by
23 articles.
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1. Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs;Applied Sciences;2023-12-20
2. A Latency-Optimized Network-on-Chip with Rapid Bypass Channels;Micromachines;2021-05-27
3. A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip;Concurrency and Computation: Practice and Experience;2020-10-12
4. Transmuter;Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques;2020-09-30
5. SMART++;Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip;2019-10-17