Advantages and Limitations of Fully on-Chip CNN FPGA-Based Hardware Accelerator-Reference-Cited by-同舟云学术

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Advantages and Limitations of Fully on-Chip CNN FPGA-Based Hardware Accelerator

Published:2020-10 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Dinelli Gianmarco,Meoni Gabriele,Rapuano Emilio,Fanucci Luca

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9179985/9180369/09180867.pdf?arnumber=9180867

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Fast and Scalable Multicore YOLOv3-Tiny Accelerator Using Input Stationary Systolic Architecture;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-11

2. Hardware Accelerated Thermal Image Processing for the Detection of Induction Motor Faults Based on Statistical Features;IECON 2023- 49th Annual Conference of the IEEE Industrial Electronics Society;2023-10-16

3. Design of Optimized CNN for Image Processing using Verilog;2023 4th IEEE Global Conference for Advancement in Technology (GCAT);2023-10-06

4. Clock Gating-Based Effectual Realization of Stochastic Hyperbolic Tangent Function for Deep Neural Hardware Accelerators;Circuits, Systems, and Signal Processing;2023-05-31

5. Design and Evaluation of Inexact Computation based Systolic Array for Convolution;2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS);2023-02-27

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