The design and implementation of the IMS A110 image and signal processor

Author:

Barraclough S.R.,Sotheran M.,Burgin K.,Wise A.P.,Vadher A.,Robbins W.P.,Forsyth R.M.

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. RNS-Based Embedded Processor Design;Embedded Systems Design with Special Arithmetic and Number Systems;2017

2. Modular multiplication using the core function in the residue number system;Applicable Algebra in Engineering, Communication and Computing;2015-07-07

3. Pipelined Two-Operand Modular Adders;Radioengineering;2015-04-15

4. An Efficient Scalable RNS Architecture for Large Dynamic Ranges;Journal of Signal Processing Systems;2014-03-13

5. High Radix Montgomery Multipliers for Residue Arithmetic Channels on FPGAs;Lecture Notes in Electrical Engineering;2011

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