Common Mode Voltage Elimination Scheme in Dual Inverter With Reduced Harmonic Distortion-Reference-Cited by-同舟云学术

Common Mode Voltage Elimination Scheme in Dual Inverter With Reduced Harmonic Distortion

Published:2023-08-10 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference on Circuit Power and Computing Technologies (ICCPCT)
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Author:

R Karthika S¹,R Vinod B¹

Affiliation:

1. College of Engineering Trivandrum, APJ Abdul Kalam Technological University,Power Electronics Research Laboratory,Dept. of Electronics and Communication Engg.,Kerala,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10244767/10244778/10245614.pdf?arnumber=10245614

Reference10 articles.

1. Voltage Harmonic Reduction using Passive Filter Shunt Passive-Active Filters for Non-linear Load;bagwari;7th International Conference on Communication Systems and Network Technologies (CSNT),0

2. A Dual Two-Level Inverter Scheme With Common Mode Voltage Elimination for an Induction Motor Drive

3. Performance for passive and active power filter in reducing harmonics in the distribution system

4. Analysis and study of total harmonic distortion in five phase PWM inverter using LC filter with neutral point DC link capacitor voltage balancing scheme

5. A High-Performance PWM Algorithm for Common-Mode Voltage Reduction in Three-Phase Voltage Source Inverters

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