Comparative Analysis of Adiabatic Logic Circuits: Power Dissipation and Performance in FPGA and ASIC Implementations of ECRL and PFAL-Reference-Cited by-同舟云学术

Comparative Analysis of Adiabatic Logic Circuits: Power Dissipation and Performance in FPGA and ASIC Implementations of ECRL and PFAL

Published:2023-08-10 Issue: Volume: Page:
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Container-title:2023 International Conference on Circuit Power and Computing Technologies (ICCPCT)
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Author:

Olanite Ayodeji¹,Ouedraogo Samuel²,Isik Murat²

Affiliation:

1. Prairie View A&M University,Electrical and Computer Eng..,Prairie View,TX

2. Drexel University,Electrical and Computer Eng.,Philadelphia,PA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10244767/10244778/10245806.pdf?arnumber=10245806

Reference17 articles.

1. ASIC Implementation of division circuit using reversible logic gates applicable in ALU s;koteswaramma;Innovations in Signal Processing and Embedded Systems Proceedings of ICISPES 2021,0

2. UL-TRA LOW POWER AND SECURE VLSI ARCHITECTURE FOR DEDICATED SHORT RANGE COMMUNICATION APPLICATIONS;kollipara;O,0

3. Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient and secure hardware

4. EE-SPFAL: A novel energy-efficient secure positive feedback adiabatic logic for DPA resistant RFID and smart card;kumar;IEEE Transactions on Emerging Topics in Computing,2016

5. EE-ACML: Energy-Efficient Adiabatic CMOS/MTJ Logic for CPA-Resistant IoT Devices

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