Author:
Dhirubhai Limbasiya Mohit,Pande Kirti S.
Cited by
7 articles.
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1. Power Efficiency Evaluation of Dual Edge Triggered Flip-Flops - A Comparative Analysis;2024 7th International Conference on Devices, Circuits and Systems (ICDCS);2024-04-23
2. Streamlined Synchronous Binary Counter with Minimized Clock Period;2023 First International Conference on Advances in Electrical, Electronics and Computational Intelligence (ICAEECI);2023-10-19
3. Robust Body Biased Level Shifter;2023 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER);2023-10-13
4. Optimized Hazard Free Pipelined Architecture Block for RV32I RISC-V Processor;2022 3rd International Conference on Smart Electronics and Communication (ICOSEC);2022-10-20
5. Reconfigurable Clock Rate Based Synchronous Binary Counter;2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon);2022-10-16