Design of High Speed 8-bit Vedic Multiplier using Brent Kung Adders-Reference-Cited by-同舟云学术

Design of High Speed 8-bit Vedic Multiplier using Brent Kung Adders

Published:2022-10-03 Issue: Volume: Page:
ISSN:
Container-title:2022 13th International Conference on Computing Communication and Networking Technologies (ICCCNT)
language:
Short-container-title:

Author:

Sai Kumar Aruru¹,Siddhesh U.¹,Sai kiran N.¹,Bhavitha K.¹

Affiliation:

1. VNR Vignana Jyothi Institute of Engineering and Technology,Department of ECE,Hyderabad,India

Publisher

IEEE

Link

Reference30 articles.

5. Development of effective method for agriculture monitoring using WSN and IOT;sai kumar;Int J of Research,2015

Cited by 28 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel Design of Area Efficient Full Adder Architecture Using Reversible Logic Gates;2024 7th International Conference on Devices, Circuits and Systems (ICDCS);2024-04-23

2. An Efficient High Performance GDI based 4-bit Vedic Multiplier in 32nm Technology;2023 Global Conference on Information Technologies and Communications (GCITC);2023-12-01

3. High performance FIR Architecture for EOG Signal Noise Supression;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06

4. Implementation of Efficient Restoring and Long Division Algorithm;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06

5. Design of DADDA Multiplier Using High Performance and Low Power Full Adder;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06