Best Practices for Compact Modeling in Verilog-A-Reference-Cited by-同舟云学术

Best Practices for Compact Modeling in Verilog-A

Published:2015-09 Issue:5 Volume:3 Page:383-396
ISSN:2168-6734
Container-title:IEEE Journal of the Electron Devices Society
language:
Short-container-title:IEEE J. Electron Devices Soc.

Author:

McAndrew Colin C.,Coram Geoffrey J.,Gullapalli Kiran K.,Jones J. Robert,Nagel Laurence W.,Roy Ananda S.,Roychowdhury Jaijeet,Scholten Andries J.,Smit Geert D. J.,Wang Xufeng,Yoshitomi Sadayuki

Funder

IEEE Electron Devices Society Technical Area Committee on Compact Modeling

NSF/SRC Nano-Engineered Electronic Device Simulation Project

Compact Model Coalition

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials,Biotechnology

Link

http://ieeexplore.ieee.org/iel7/6245494/7217859/07154394.pdf

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