A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators-Reference-Cited by-同舟云学术

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A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators

Published:2020-10 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE 38th International Conference on Computer Design (ICCD)
language:
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Author:

Xu Dawen,Chu Cheng,Wang Qianlong,Liu Cheng,Wang Ying,Zhang Lei,Liang Huaguo,Cheng Kwang-Ting

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9282809/9283502/09283550.pdf?arnumber=9283550

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks;ACM Computing Surveys;2024-01-22

2. An Efficient Fault Tolerance Strategy for Multi-task MapReduce Models Using Coded Distributed Computing;Lecture Notes in Computer Science;2024

3. Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses;ACM Transactions on Design Automation of Electronic Systems;2023-07-18

4. STRIVE: Enabling Choke Point Detection and Timing Error Resilience in a Low-Power Tensor Processing Unit;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

5. DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs’ Reliability Assessment;2023 IEEE European Test Symposium (ETS);2023-05-22

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