Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages
Author:
Affiliation:
1. IHP-Leibniz-Institut für innovative Mikroelektronik,Frankfurt (Oder),Germany
Funder
Ministry of Education
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9962319/9962334/09962345.pdf?arnumber=9962345
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Compensation architecture design utilizing residual resource to mitigate impacts of nonidealities in RRAM-based computing-in-memory chips;Microelectronics Journal;2024-07
2. Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment;2024 IEEE 25th Latin American Test Symposium (LATS);2024-04-09
3. Towards Reliable and Energy-Efficient RRAM Based Discrete Fourier Transform Accelerator;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
4. LUT-based RRAM Model for Neural Accelerator Circuit Simulation;Proceedings of the 18th ACM International Symposium on Nanoscale Architectures;2023-12-18
5. Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26
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