Author:
Andrade Joao,Pratas Frederico,Falcao Gabriel,Silva Vitor,Sousa Leonel
Cited by
9 articles.
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1. TLP-LDPC: Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis;Journal of Computer Science and Technology;2022-11-30
2. A Code Rate-Compatible High-Throughput Hardware Implementation Scheme for QKD Information Reconciliation;Journal of Lightwave Technology;2022-06-15
3. Performance Balanced General Decoder Design for QC-LDPC Codes Using Vivado HLS;2021 IEEE 11th International Conference on Electronics Information and Emergency Communication (ICEIEC)2021 IEEE 11th International Conference on Electronics Information and Emergency Communication (ICEIEC);2021-06-18
4. Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices;Journal of Signal Processing Systems;2020-02-13
5. Performance Analysis with Cache-Aware Roofline Model in Intel Advisor;2017 International Conference on High Performance Computing & Simulation (HPCS);2017-07