High-speed CRC computations using improved state-space transformations

Author:

Kennedy Christopher,Reyhani-Masoleh Arash

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Analysis of an Efficient Fault Tolerant Linear Feedback Shift Register for Low Power Applications;2024 10th International Conference on Communication and Signal Processing (ICCSP);2024-04-12

2. Parallel CRC On An FPGA At Terabit Speeds;2022 International Conference on Field-Programmable Technology (ICFPT);2022-12-05

3. Low-Complexity Parallel Cyclic Redundancy Check;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05

4. Low-Complexity Architectures for Parallel Long BCH Encoders;2020 IEEE Workshop on Signal Processing Systems (SiPS);2020-10

5. A Low-Power Parallel Architecture for Linear Feedback Shift Registers;IEEE Transactions on Circuits and Systems II: Express Briefs;2019-03

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