Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices-Reference-Cited by-同舟云学术

Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices

Published:2023-03 Issue:3 Volume:31 Page:320-330
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Parmar Rushik¹^ORCID,Janveja Meenali¹^ORCID,Pidanic Jan²^ORCID,Trivedi Gaurav¹^ORCID

Affiliation:

1. Department of Electronics and Electrical Engineering, IIT Guwahati, Guwahati, India

2. Department of Electrical Engineering, Faculty of Electrical Engineering and Informatics, University of Pardubice, Pardubice, Czech Republic

Funder

Electronics and ICT Academy at IIT Guwahati

Ministry of Electronics and Information Technology, India

Programme INTER-EXCELLENCE

Ministry of Education, Youth and Sports, Czech Republic, “Artificial Intelligence Enabled Smart Contact-less Technology Development for Smart Fencing”

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/10049803/10021279.pdf?arnumber=10021279

Reference33 articles.

1. Automatic detection of atrial fibrillation using stationary wavelet transform and support vector machine

2. Classification of Paroxysmal and Persistent Atrial Fibrillation in Ambulatory ECG Recordings

3. An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications

4. Cardiac Rhythm Classification from a Short Single Lead ECG Recording via Random Forest

5. A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65 nm CMOS;andersson;Proc IEEE Int Symp Circuits Syst (ISCAS),2015

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