OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks-Reference-Cited by-同舟云学术

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OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks

Published:2020-01 Issue:1 Volume:28 Page:35-47
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Yu Yunxuan^ORCID,Wu Chen,Zhao Tiandong,Wang Kun,He Lei^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8945454/08863128.pdf?arnumber=8863128

Cited by 93 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Graph-OPU: A highly flexible FPGA-Based Overlay Processor for Graph Neural Networks;ACM Transactions on Reconfigurable Technology and Systems;2024-09-02

2. Graph Neural Networks with Autoregressive Moving Average Graph Filter and Graph- Regularized Sparse Coding for Accurate Hyperspectral Image Classification on FPGA;2024-08-05

3. RAMAN: A Reconfigurable and Sparse tinyML Accelerator for Inference on Edge;IEEE Internet of Things Journal;2024-07-15

4. An Architectural Template for FPGA Overlays Targeting Data Flow Applications;2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2024-05-27

5. DNNMapper: An Elastic Framework for Mapping DNNs to Multi-die FPGAs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

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