A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM-Reference-Cited by-同舟云学术

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A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM

Published:2016-03 Issue:3 Volume:24 Page:968-978
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Joshi Rajiv,Saroop Sudesh,Kanj Rouwaida,Liu Yang,Wang Weike,Radens Carl,Tan Yue,Yogendra Karthik

Funder

U.S. Defense Advanced Research Projects Agency’s PERFECT Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7416268/7118750.pdf?arnumber=7118750

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. (Invited) Predictive analytics for cryogenic CMOS in future quantum computing systems;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

2. Cryogenic CMOS: design considerations for future quantum computing systems;2023 IEEE Custom Integrated Circuits Conference (CICC);2023-04

3. Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-12

4. SOPA: Search Optimization Based Predictive Approach for Design Optimization in FinFET/SRAM;Advances in Intelligent Systems and Computing;2018-05-27

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