135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder

Author:

Li Gwo-Long,Chen Tzu-Yu,Shen Meng-Wei,Wen Meng-Hsun,Chang Tian-Sheuan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Optimized Inter Prediction for H.264 Video Codec;International Journal of Electronics and Telecommunications;2023-07-26

2. Optimized Solution to Accelerate in Hardware an Intra H.264/SVC Video Encoder;IEEE Micro;2018-11-01

3. A low-complexity MPEG-2 to H.264/AVC wavefront intra-frame transcoder architecture;Journal of Real-Time Image Processing;2016-05-03

4. Enhanced pipelined architecture of H.264/AVC intra prediction;Signal Processing: Image Communication;2016-02

5. An MPEG-2 to H.264/AVC intra-frame transcoder architecture with mode decision in transform domain;IEEE Transactions on Consumer Electronics;2015-02

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