Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus-Reference-Cited by-同舟云学术

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Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus

Published:2009-08 Issue:8 Volume:17 Page:1034-1047
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Junhee Yoo ,Sungjoo Yoo ,Kiyoung Choi

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/5170177/04982672.pdf?arnumber=4982672

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Reconfigurable Design of Flexible-arbitrated Crossbar Interconnects in Multi-core SoC system;2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2022-12

2. Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs;2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2016-07

3. Design automation for application-specific on-chip interconnects: A survey;Integration;2016-01

4. Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects;ACM Transactions on Embedded Computing Systems;2015-05-21

5. Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis;IEEE Transactions on Computers;2014-06

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