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Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes

  • Published:2014-11 Issue:11 Volume:22 Page:2256-2267
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Garcia-Herrero Francisco,Li Erbao,Declercq David,Valls Javier

Funder

Spanish Ministerio de Ciencia e Innovación

Universitat Politècnica de València

Institut Universitaire de France

Spanish Government, Ministerio de Educación

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Trapping and Absorbing Set Enumerators for Nonbinary Protograph-Based Low-Density Parity-Check Code Ensembles;IEEE Transactions on Communications;2023-04

2. Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension;IEEE Transactions on Aerospace and Electronic Systems;2023

3. A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA and GPU Architectures;IEEE Communications Surveys & Tutorials;2021

4. An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018-05

5. A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications;IEEE Transactions on Circuits and Systems II: Express Briefs;2018-02
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