Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area-Reference-Cited by-同舟云学术

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Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area

Published:2012-12 Issue:12 Volume:20 Page:2333-2337
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Kim Nam Sung,Draper Stark C.,Zhou Shi-Ting,Katariya Sumeet,Ghasemi Hamid Reza,Park Taejoon

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/6257480/06081976.pdf?arnumber=6081976

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