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A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

  • Published:2016-02 Issue:2 Volume:24 Page:789-793
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Kim Yong-Hun,Kim Young-Ju,Lee Taeho,Kim Lee-Sup

Funder

IC Design Education Center

Basic Science Research Program through the National Research Foundation of Korea within the Ministry of Science, ICT and Future Planning

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

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