Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements-Reference-Cited by-同舟云学术

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Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Published:2013-03 Issue:3 Volume:21 Page:454-464
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Kook Sehun,Choi Hyun Woo,Chatterjee Abhijit

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/6466554/06193234.pdf?arnumber=6193234

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low-Cost Linearity Testing of High-Resolution ADCs Using Segmentation Modeling and Partial Polynomial Fitting;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Methods to Improve Linearity of Signal’s Analog-to-Digital Conversion with Self-Calibration;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31

3. Wavelet decomposition and reconstruction-based INL method for testing high-precision ADC;Microelectronics Journal;2023-12

4. An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-11

5. Fault steady-state analysis method for the AC system with LCC-HVDC infeed;Electric Power Systems Research;2021-03

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