Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations

Author:

Zarandi Azadeh Alsadat Emrani,Molahosseini Amir Sabbagh,Hosseinzadeh Mehdi,Sorouri Saeid,Antao Samuel,Sousa Leonel

Funder

National Funds through Fundação para a Ciência e a Tecnologia

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Generalized Residue Number System Design Approach for Ultralow-Power Arithmetic Circuits Based on Deterministic Bit-Streams;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

2. Improving the Parallelism and Balance of RNS with Low-Cost and $$2^{{\varvec{k}}} + 1$$ Modules;Current Problems in Applied Mathematics and Computer Science and Systems;2023

3. Energy-Efficient Residue-to-Binary Conversion Based on a Modulo-Adder-Free Architecture;2022 30th International Conference on Electrical Engineering (ICEE);2022-05-17

4. A Fast-Transient Response Digital Low-Dropout Regulator With Dual-Modes Tuning Technique;IEEE Transactions on Circuits and Systems II: Express Briefs;2020-12

5. Efficient programmable power‐of‐two scaler for the three‐moduli set {2 n + p , 2 n  − 1, 2 n +1  − 1};ETRI Journal;2020-05-27

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