A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array

Author:

Kulkarni Jaydeep P.,Goel Ashish,Ndai Patrick,Roy Kaushik

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 33 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. Computation-in-Memory Based Boolean Circuit Design Using Tunnel FET Based 8T SRAM;2024 International Conference on Distributed Computing and Optimization Techniques (ICDCOT);2024-03-15

3. A Low Power and Reduced Delay SRAM Cell for Biomedical Applications;2023 International Conference on Data Science and Network Security (ICDSNS);2023-07-28

4. Comparative Validation of SRAM Cells Based on Decoupled Read Technique using 45nm CMOS;2023 IEEE 12th International Conference on Communication Systems and Network Technologies (CSNT);2023-04-08

5. 9T SRAM Cell for Computation-In-Memory Architectures: Proposal & Investigation;2023 IEEE Devices for Integrated Circuit (DevIC);2023-04-07

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