A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops-Reference-Cited by-同舟云学术

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A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops

Published:2021-05 Issue:5 Volume:29 Page:998-1008
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Centurelli Francesco^ORCID,Scotti Giuseppe^ORCID,Palumbo Gaetano^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/9416715/09363274.pdf?arnumber=9363274

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A New Source-Coupled Logic Technique: ALSCL;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04

2. Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved Multiple-Tail Current Mode Logic;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-11

3. Design of current steering logic CMOS circuit;Microelectronics Journal;2023-11

4. Simple and Accurate Model for the Propagation Delay in MCML Gates;Electronics;2023-06-15

5. Design and simulation of compact graphene-based plasmonic flip-flop using a resonant ring;Diamond and Related Materials;2023-06

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