High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers-Reference-Cited by-同舟云学术

High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers

Published:2022-04 Issue:4 Volume:30 Page:544-548
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Lyu Fei¹^ORCID,Xia Yan²,Chen Yuheng²,Wang Yanxu²,Luo Yuanyong³^ORCID,Wang Yu²

Affiliation:

1. School of Electronics and Information Engineering, Jinling Institute of Technology, Nanjing, China

2. School of Electronics Engineering, Nanjing Xiaozhuang University, Nanjing, China

3. Department of Turing Architecture Design, Linx Laboratory, HiSilicon, Huawei Corporation, Shenzhen, China

Funder

Natural Science Foundation of the Jiangsu Higher Education Institutions of China

Scientific Research Foundation for the High-Level Talents of Jinling Institute of Technology

Scientific Research Incubation Foundation of Jinling Institute of Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

Reference10 articles.

1. High-speed floating-point divider with reduced area;han;Proc SPIE Math Signal Inf Process,2009

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