A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC-Reference-Cited by-同舟云学术

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A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC

Published:2017-05 Issue:5 Volume:25 Page:1742-1755
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Cho Je-Kwang^ORCID,Woo Sunsik

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7909068/07839317.pdf?arnumber=7839317

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Systematic Method for Scaling Coefficients of the Continuous-Time Low-Pass ΣΔ Modulator Using a Simulink-Based Toolbox;Eng;2023-12-19

2. A New Noise Shaping Approach for Sigma-Delta Modulators Using Two-Stage Feed-Forward Delays and Hybrid MASH-EFM;Electronics;2023-02-01

3. A 4th-Order 4-Bit Continuous-Time ΔΣ ADC Based on Active–Passive Integrators With a Resistance Feedback DAC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-06

4. Continuous-Time Delta-Sigma Converters with Finite-Impulse-Response (FIR) Feedback;Next-Generation ADCs, High-Performance Power Management, and Technology Considerations for Advanced Integrated Circuits;2019-10-25

5. A 2-MHz BW 82-dB DR Continuous-Time Delta–Sigma Modulator With a Capacitor-Based Voltage DAC for ELD Compensation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-10

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