Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory-Reference-Cited by-同舟云学术

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Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory

Published:2013-06 Issue:6 Volume:21 Page:1094-1102
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Hu Jingtong,Xue Chun Jason,Zhuge Qingfeng,Tseng Wei-Che,Sha Edwin H.-M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/6517540/06248275.pdf?arnumber=6248275

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2. Optimizing Data Placement for Hybrid SRAM+Racetrack Memory SPM in Embedded Systems;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-03

3. Loop interchange and tiling for multi-dimensional loops to minimize write operations on NVMs;Journal of Systems Architecture;2023-02

4. Optimal Loop Tiling for Minimizing Write Operations on NVMs with Complete Memory Latency Hiding;2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC);2022-01-17

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