A High-Speed Low-Complexity Modified ${\rm Radix}-2^{5}$ FFT Processor for High Rate WPAN Applications-Reference-Cited by-同舟云学术

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A High-Speed Low-Complexity Modified ${\rm Radix}-2^{5}$ FFT Processor for High Rate WPAN Applications

Published:2013-01 Issue:1 Volume:21 Page:187-191
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Cho Taesang,Lee Hanho

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/6387661/06145762.pdf?arnumber=6145762

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3. Area efficient VLSI architecture for reversible radix_2 FFT algorithm;2021 International Conference on Emerging Smart Computing and Informatics (ESCI);2021-03-05

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5. A low-complexity design for the terminal device of the urban IoT-oriented heterogeneous network with ultra-high-speed OFDM processing;Sustainable Cities and Society;2020-10

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