Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs

Author:

Ganusov Ilya,Fraisse Henri,Ng Aaron,Possignolo Rafael Trapani,Das Sabya

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. 3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. FPGA-Based Control of Remote Robotic Hands and ROS2 Integration;2022 Tenth International Symposium on Computing and Networking Workshops (CANDARW);2022-11

3. Optimizing FPGA-Based Streaming Applications for Throughput Using Pipelining;2019 International Conference on Field-Programmable Technology (ICFPT);2019-12

4. Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx FPGAs;2019 29th International Conference on Field Programmable Logic and Applications (FPL);2019-09

5. SMatch;Proceedings of the 56th Annual Design Automation Conference 2019;2019-06-02

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