Detailed routing violation prediction during placement using machine learning-Reference-Cited by-同舟云学术

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Detailed routing violation prediction during placement using machine learning

Published:2017-04 Issue: Volume: Page:
ISSN:
Container-title:2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
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Author:

Tabrizi Aysa Fakheri,Darav Nima Karimpour,Rakai Logan,Kennings Andrew,Behjat Laleh

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7936426/7939640/07939657.pdf?arnumber=7939657

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Implement a PnR Flow to Boost the Pin Density in Block Level Chip Design;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28

2. Design of Digital Integrated Circuits by Improving the Characteristics of Digital Cells;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31

3. DRC Violation Prediction After Global Route Through Convolutional Neural Network;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-09

4. DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05

5. Progress of Placement Optimization for Accelerating VLSI Physical Design;Electronics;2023-01-09

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