An all-digital delay-locked loop for high-speed memory interface applications
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6823815/6834858/06834900.pdf?arnumber=6834900
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Wide-Range and High-Linearity Timing Generator with 1.25ps-Resolution;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20
2. Physical Implementation of Low-Power Area-efficient Digital Delay Locked Loop for High-Speed Interface in Sub -10nm Technology;2022 International Conference on Computing, Electronics & Communications Engineering (iCCECE);2022-08-17
3. A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing;Lecture Notes in Computer Science;2019
4. Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines;Circuits, Systems, and Signal Processing;2016-07-27
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