Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse-Reference-Cited by-同舟云学术

Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse

Published:2018-03 Issue:1 Volume:8 Page:116-124
ISSN:2156-3357
Container-title:IEEE Journal on Emerging and Selected Topics in Circuits and Systems
language:
Short-container-title:IEEE J. Emerg. Sel. Topics Circuits Syst.

Author:

Chang Chih-Cheng^ORCID,Chen Pin-Chun,Chou Teyuh^ORCID,Wang I-Ting,Hudec Boris^ORCID,Chang Che-Chia,Tsai Chia-Ming,Chang Tian-Sheuan^ORCID,Hou Tuo-Hung^ORCID

Funder

Ministry of Science and Technology of Taiwan

Research of Excellence Program

Taiwan Semiconductor Manufacturing Company

NCTU-UCB I-RiCE Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/5503868/8330765/08101463.pdf?arnumber=8101463

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